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Technology and characterisation of ultrathin PECVD silicon layers for nanoelectronic structures

2011/03/B/ST7/02595

Keywords:

silicon nanoelectronics silicon technology PECVD quantum devices

Descriptors:

  • ST7_5: Micro- and nanelectronic, optoelectronic and photonic components

Panel:

ST7 - Systems and communication engineering: electronics, communication, optoelectronics

Host institution :

Politechnika Warszawska, Wydział Elektroniki i Technik Informacyjnych

woj. mazowieckie

Other projects carried out by the institution 

Principal investigator (from the host institution):

prof. Romuald Beck 

Number of co-investigators in the project: 17

Call: OPUS 2 - announced on 2011-09-15

Amount awarded: 598 720 PLN

Project start date (Y-m-d): 2012-08-30

Project end date (Y-m-d): 2016-02-29

Project duration:: 42 months (the same as in the proposal)

Project status: Project settled

Information in the final report

  • Publication in academic press/journals (7)
  • Articles in post-conference publications (11)
  1. Charging/discharging processes in nanocrystaline MOS structures - Theoretical study
    Authors:
    D. Tanous, A. Mazurak, B. Majkusiak
    Academic press:
    Journal of Physics - Conference Series (rok: 2016, tom: -, strony: -), Wydawca: -
    Status:
    Published
    DOI:
    10.1088/issn.1742-6596 - link to the publication
  2. Effects of Inner Interface Traps on High-K Gate Stack Devices Admittance Characteristics
    Authors:
    Andrzej Mazurak, Jakub Jasiński, Bogdan Majkusiak
    Academic press:
    IEEE Xplore Digital Liberary (rok: 2016, tom: brak, strony: 194-197), Wydawca: IEEE
    Status:
    Published
    DOI:
    brak - link to the publication
  3. Description of tunneling through a metal-insulator-metal junction considering Coulomb Blockade
    Authors:
    D. Tanous, B. Majkusiak
    Academic press:
    Proc. of SPIE (rok: 2013, tom: vol. 8902, strony: 89020P-1 do 8), Wydawca: Eds. P. Szczepański, R. Kisiel, R.S. Romaniuk - SPIE
    Status:
    Published
    DOI:
    10.1117/12.2031274 - link to the publication
  4. Recrystallization and oxidation - competing processes during PECVD ultrathin silicon layer high temperature annealing
    Authors:
    Romuald B. Beck; Kamil Ber
    Academic press:
    IEEE Xplore Digital Liberary (rok: 2016, tom: brak, strony: 190-193), Wydawca: IEEE
    Status:
    Published
    DOI:
    brak - link to the publication
  5. Small-signal admittance model of multi-traps distributed over energy and space in the insulator of MIS tunnel structures
    Authors:
    J. Jasiński, A. Mazurak, R. Mroczyński, B. Majkusiak
    Academic press:
    Microelectronic Engineering (rok: 2015, tom: 147, strony: 349-353), Wydawca: Elsevier
    Status:
    Published
    DOI:
    0.1016/j.mee.2015.04.100 - link to the publication
  6. Effects of non-stoichiometry of silicon oxide layers in double barrier structure on high temperature annealing of ultrathin silicon layer
    Authors:
    R.B. Beck and P. Korb
    Academic press:
    IEEE Xplore Digital Library (rok: 2017, tom: brak, strony: 45295), Wydawca: IEEE
    Status:
    Published
    DOI:
    10.1109/ULIS.2017.7962573 - link to the publication
  7. Formation of ultrathin silicon layers by PECVD and their modification for nanoelectronic and nanophotonic applications
    Authors:
    Kamil Ber, Romuald B Beck
    Academic press:
    Proc. of SPIE (rok: 2013, tom: 8902, strony: 89022A1-10), Wydawca: Eds. P. Szczepański, R. Kisiel, R.S. Romaniuk - SPIE
    Status:
    Published
    DOI:
    10.1117/12.2030884 - link to the publication
  1. Effect of Inner Interface Traps on High-K Gate Stack Devices Admittance Characteristics
    Authors:
    A. Mazurak, J. Jasiński, B. Majkusiak
    Conference:
    2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (rok: 2016, ), Wydawca: Society for Micro- and Nanoelectronics c/o Techniche Universitat Wien
    Data:
    konferencja January 25-27 2016
    Status:
    Published
  2. Recrystallization and Oxidation - Competing Processes during PECVD Ultrathin SIliocn Layer High Temperature Annealing
    Authors:
    Romuald B. Beck; Kamil Ber
    Conference:
    2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (rok: 2016, ), Wydawca: Society for Micro- and Nanoelecotrnics c/o Techniche Universitat Wien
    Data:
    konferencja Januar 25-27 2016
    Status:
    Published
  3. Charging/discharging processes in nanocrystaline MOS structures - Theoretical study
    Authors:
    D. Tanous, A. Mazurak, B. Majkusiak
    Conference:
    MICROTECHNOLOGY AND THERMAL PROBLEMS IN ELECTRONICS (MICROTHERM 2015), 23 - 25 VI 2015 Łódź (rok: 2015, ), Wydawca: Lodz University of Technology
    Data:
    konferencja 23-25.07.2015
    Status:
    Published
  4. Effects of non-stoichiometry of silicon oxide layers in double barrier structure on high temperature annealing of ultrathin silicon layer
    Authors:
    R.B. Beck and P. Korb
    Conference:
    2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (rok: 2017, ), Wydawca: Society for Micro- and Nanoelectronics c/o Institute on Nanoscience and Nanotechnology, NCSR "Demokritos" Athens
    Data:
    konferencja April 3-5 2017
    Status:
    Published
  5. Study of the effect of tunneling through the traps inside the insulator on small-signal admittance on the MOS structure
    Authors:
    J. Jasiński, A. Mazurak, B. Majkusiak
    Conference:
    18th Conference on Insulating Films on Semiconductor - INFOS'2013 (rok: 2013, ), Wydawca: Eds. L. Łukasiak, J. Grabowski - Oficyna Wydawnicza PW
    Data:
    konferencja 25-28 June 2013
    Status:
    Published
  6. Theoretical andExperimental Investigation of ncMOS Structures with Ge nanocrystals for Memory and Photonic Applications
    Authors:
    D. Tanous, A. Mazurak, B. Majkusiak, R. Beyer
    Conference:
    18th Workshop on Dielectrics ini Microelectronics, WODIM 2014 (rok: 2014, ), Wydawca: Tyndall National Institute
    Data:
    konferencja 9-11 June 2014
    Status:
    Published
  7. Analysis of competing processes of oxidation and recrystallization of amorphous silicon layers in double dielectric barrier ultra-thin structures
    Authors:
    K. Ber, R.B. Beck
    Conference:
    18th Workshop on Dielectrics in Microelectronics, WODIM 2014 (rok: 2014, ), Wydawca: Tyndall National Institute
    Data:
    konferencja 9-11 June 2014
    Status:
    Published
  8. Wytwarzanie ultracienkich warstw krzemowych metodą PECVD i ich modyfikacja dla potrzeb nanoelektroniki i nanofotoniki
    Authors:
    K. Ber, R.B. Beck
    Conference:
    XI Konferencja Naukowa Technologia Elektronowa ELTE'2013 (rok: 2013, ), Wydawca: Eds. P. Szczepański, R. Piramidowicz - Poliechnika Warszawska
    Data:
    konferencja 16-20 2013r.
    Status:
    Published
  9. Effects of High Temperature Annealing of Double Barrier Structure with Ultrathin PECVD Silicon and Non-Stoichiometric Oxide Layers
    Authors:
    R.B. Beck. P. Korb
    Conference:
    XII Konferencja Naukowa Technologia Elektronowa ELTE'2016 (rok: 2016, ), Wydawca: AGH Kraków
    Data:
    konferencja 11-14 września 2016r.
    Status:
    Published
  10. Ellipsometric spectroscopy as a tool for investigation of nanocrystals in ultrathin PECVD silicon layers' behavior during high temperature annealing
    Authors:
    R.B. Beck, P. Korb and K. Ber
    Conference:
    E-MRS Fall Meeting 2016 (rok: 2016, ), Wydawca: E-MRS
    Data:
    konferencja 19-22 September 2016
    Status:
    Published
  11. Small-signal admittance model of multi-traps distributed over energy and space in the insulator of MIS tunnel structures
    Authors:
    J. Jasiński, A. Mazurak, R. Mroczyński, B. Majkusiak
    Conference:
    19th Conference on "Insulating Films on Semiconductors" (INFOS 2015), 29 VI - 2 VII 2015, Udine, Włochy (rok: 2015, ), Wydawca: Conference Organizing Committee
    Data:
    konferencja 29 VI - 2 VII 2015
    Status:
    Published

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