2023/51/B/ST7/01782
Keywords:
design of integrated circuits VLSI technology
Descriptors:
Panel:
ST7 - Systems and communication engineering: electronics, communication, optoelectronics
Host institution :
Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie, Wydział Elektrotechniki, Automatyki, Informatyki i Inżynierii Biomedycznej
woj. małopolskie
Principal investigator (from the host institution):
Number of co-investigators in the project: 7
Call: OPUS 26 - announced on 2023-09-18
Amount awarded: 2 891 000 PLN
Project start date (Y-m-d): 2024-07-10
Project end date (Y-m-d): 2027-07-09
Project duration:: 36 months (the same as in the proposal)
Project status: Pending project
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