2015/17/N/ST7/03720
Keywords:
Power electronics PWM voltage source inverter output filter pole-placement design coefficient diagram method repetitive controller deadbeat control small signal model discrite model impedance networks ZSI qZSI SIZSI CqZSI LCCT-ZSI multi loop control system THD UPS properties of magnetic materials
Descriptors:
Panel:
ST7 - Systems and communication engineering: electronics, communication, optoelectronics
Host institution :
Politechnika Śląska, Wydział Automatyki, Elektroniki i Informatyki
woj. śląskie
Principal investigator (from the host institution):
Number of co-investigators in the project: 2
Call: PRELUDIUM 9 - announced on 2015-03-16
Amount awarded: 94 900 PLN
Project start date (Y-m-d): 2016-03-16
Project end date (Y-m-d): 2018-09-15
Project duration:: 30 months (the same as in the proposal)
Project status: Project settled
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