2011/01/B/ST7/06120
Keywords:
constant coefficient FIR filters digital signal processing residue number system arithmetic circuits residue number system application specific integrated circuits (ASIC) very large scale integration (VLSI)
Descriptors:
Panel:
ST7 - Systems and communication engineering: electronics, communication, optoelectronics
Host institution :
Politechnika Wrocławska, Wydział Elektroniki
woj. dolnośląskie
Principal investigator (from the host institution):
Number of co-investigators in the project: 5
Call: OPUS 1 - announced on 2011-03-15
Amount awarded: 399 000 PLN
Project start date (Y-m-d): 2011-12-07
Project end date (Y-m-d): 2015-10-06
Project duration:: 46 months (the same as in the proposal)
Project status: Project settled