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Information on the principal investigator and host institution

Information of the project and the call

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Electrical characterization of the advanced MIS structures in the range of low and very low frequencies.

2012/07/N/ST7/03233

Keywords:

multilayer dielectrics nanocrystallies low frequency characterization admittance characterization tunneling

Descriptors:

  • ST7_5: Micro- and nanelectronic, optoelectronic and photonic components

Panel:

ST7 - Systems and communication engineering: electronics, communication, optoelectronics

Host institution :

Politechnika Warszawska, Wydział Elektroniki i Technik Informacyjnych

woj. mazowieckie

Other projects carried out by the institution 

Principal investigator (from the host institution):

dr Jakub Jasiński 

Number of co-investigators in the project: 3

Call: PRELUDIUM 4 - announced on 2012-09-15

Amount awarded: 123 700 PLN

Project start date (Y-m-d): 2013-07-18

Project end date (Y-m-d): 2016-02-17

Project duration:: 31 months (the same as in the proposal)

Project status: Project settled

Equipment purchased [PL]

  1. Komputer z drukarką oraz uzupełniający drobny sprzęt (4 000 PLN)
  2. Przedwzmacniacze KEITHLEY 4200-PA wraz z okablowaniem (2 szt.) (17 000 PLN)

Information in the final report

  • Publication in academic press/journals (2)
  • Articles in post-conference publications (2)
  1. Small-signal admittance model of multi-traps distributed over energy and space in the insulator of MIS tunnel structures
    Authors:
    Jakub Jasiński, Andrzej Mazurak, Robert Mroczyński, Bogdan Majkusiak
    Academic press:
    Microelectronic Engineering (rok: 2015, tom: 147, strony: 349-353), Wydawca: Elsevier
    Status:
    Published
    DOI:
    10.1016/j.mee.2015.04.100 - link to the publication
  2. Effect of Inner Interface Traps on High-K Gate Stack Admittance Characteristics
    Authors:
    A. Mazurak, J. Jasiński, B. Majkusiak
    Academic press:
    IEEE Xplore (rok: 2016, tom: -, strony: 194-197), Wydawca: IEEE
    Status:
    Published
    DOI:
    10.1109/ULIS.2016.7440086 - link to the publication
  1. Effect of Inner Interface Traps on High-K Gate Stack Devices Admittance Characteristics
    Authors:
    A. Mazurak, J. Jasiński, B. Majkusiak
    Conference:
    2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon EUROSOI-ULIS 2016 (rok: 2016, ), Wydawca: Institute for Microelectronics TU Wien
    Data:
    konferencja 25-17 stycznia 2016
    Status:
    Published
  2. Small-signal admittance model of multi-traps distributed over energy and space in the insulator of MIS tunnel structures
    Authors:
    J. Jasiński, A. Mazurak, R. Mroczyński, B.Majkusiak
    Conference:
    19th Insulating Films on Semiconductors" INFOS 2015 (rok: 2015, ), Wydawca: University of Udine
    Data:
    konferencja 29 czerwca - 2 lipca 2015
    Status:
    Published

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