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Development of novel ultra-low power, multichannel analog-to-digital conversion system with fast data serialization, in deep sub-micron technologies

2012/07/B/ST7/01456

Keywords

Descriptors

  • ST7_5: Mikro- i nanoelektronika, optoelektronika
  • ST7_2: Elektrotechnika, elektronika: półprzewodniki, elementy i układy, systemy
  • ST7_7: Przetwarzanie sygnałów

Panel

ST7 – Systems and communication engineering: electronics, communication, optoelectronics

Host institution

Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie, Wydział Fizyki i Informatyki Stosowanej

Voivodeship: małopolskie

Other projects carried out by the institution »

Principal investigator (from the host institution)

prof. Marek Idzik

Number of co-investigators in the project: 8

Call

OPUS 4 – announced on 2012-09-15

Amount awarded
1 224 600 PLN
Project start date
2013-07-08
Project end date
2018-04-07
Project duration
57 months (the same as in the proposal)
Project status
Project settled

Information in the final report

Publication in academic press/journals (4)

  1. A wide range ultra-low power Phase-Locked Loop with automatic frequency setting in 130 nm CMOS technology for data serialisation

    Authors:
    M. Firlej, T. Fiutowski, M. Idzik, J. Moron and K. Swientek
    Academic press:
    Journal of Instrumentation (year: 2015, volume: JINST 10 P12015, pages: 46036), Publisher: International School for Advanced Studies (SISSA) and the Institute of Physics Publishing (IOP Publishing)
    Status:
    Published
    DOI:
    10.1088/1748-0221/10/12/P12015 – link to the publication

  2. 1. A fast, ultra-low and frequency-scalable power consumption, 10-bit SAR ADC for particle physics detectors

    Authors:
    M.Firlej, T.Fiutowski, M.Idzik, Sz. Kulis, J.Moron, K. Swientek
    Academic press:
    Journal of Instrumentation (year: 2015, volume: JINST 10 P11012, pages: 46040), Publisher: International School for Advanced Studies (SISSA) and the Institute of Physics Publishing (IOP Publishing)
    Status:
    Published
    DOI:
    10.1088/1748-0221/10/11/P11012 – link to the publication

  3. Development of a low power Delay-Locked Loop in two 130 nm CMOS technologies

    Authors:
    Miroslaw Firlej, Tomasz Fiutowski, Marek Idzik, Jakub Moron, Krzysztof Swientek
    Academic press:
    Journal of Instrumentation (year: 2016, volume: JINST 11 C02027, pages: 46031), Publisher: International School for Advanced Studies (SISSA) and the Institute of Physics Publishing (IOP Publishing)
    Status:
    Published
    DOI:
    10.1088/1748-0221/11/02/C02027 – link to the publication

  4. Ultra-Low Power Fast Multi-Channel 10-Bit ADC ASIC for Readout of Particle Physics Detectors

    Authors:
    S. Bugiel, R. Dasgupta, M. Firlej, T. Fiutowski, M. Idzik, M. Kopec, J. Moron, and K. Swientek
    Academic press:
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE (year: 2016, volume: 63, pages: 2622-2631), Publisher: IEEE
    Status:
    Published
    DOI:
    10.1109/TNS.2016.2602391 – link to the publication

Articles in post-conference publications (1)

  1. A fast, low-power, multichannel 6-bit ADC ASIC with data serialisation

    Authors:
    M. Firlej, T. Fiutowski, M. Idzik, J. Moron, K. Swientek
    Conference:
    International conference on Technology and Instrumentation in Particle Physics TIPP'14 (year: 2014, pages: 46030), Publisher: Proceedings of Science
    Date:
    conference 2-6 June
    Status:
    Published
    DOI:
    link to the publication

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Graphic design and implementation: Jakub Piotrowski